The present invention relates to an ESD protection device for electronic devices protecting against electrostatic discharges, so-called ESD protection devices, and in particular to such ESD protection devices for integrated circuits (ICs; IC=Integrated Circuit).
For providing an ESD protection for integrated circuits it is, for example, known to use transistors whose drain electrode and gate electrode are actively clamped by means of Zener diodes. Such known ESD protection devices require, however, much space and entail therefore high costs.
DE 693 11 001 T2 discloses a diode structure for protecting IC terminals, which comprises two diodes, one of these diodes being connected between a ground potential and the connection between a connection surface of the IC and the IC to be protected. The second diode is connected between a supply voltage potential and the above-mentioned connection. The two diodes are respectively connected with different polarities so that the first diode is poled for negative voltages in the direction of flow, whereas the second diode is poled for positive voltages in the direction of flow. The respective diodes are conventional pn-diodes with a lightly doped pn-junction, the connection regions of the pn-diodes being heavily doped.
U.S. Pat. No. 5,521,783 refers to a two-stage circuit used for protecting against electrostatic discharges, the first stage being defined by a transistor with a high breakthrough voltage, whereas the second stage is defined by a transistor with a low breakthrough voltage.
It is the object of the present invention to provide an ESD protection device for integrated circuits, which requires less space and which is therefore less expensive.
This object is achieved by an ESD protection device for integrated circuits according to claims 1 and 5.
The present invention provides an ESD protection device for an integrated circuit, which is integrated in a semiconductor substrate of the integrated circuit. The protection device comprises a heavily doped region of a first doping type, which is provided with a first connection electrode as well as a heavily doped region of a second doping type, which is provided with a second connection electrode. A lightly doped region of a first doping type borders on the heavily doped region of the first doping type, whereas a lightly doped region of the second doping type borders on the heavily doped region of the second doping type and the lightly doped region of the first doping type in such a way that the lightly doped regions are arranged at least between the heavily doped regions. The distance which exists between the lightly doped region of the first doping type and the heavily doped region of the second doping type and which is determined by the lightly doped region of the second doping type is now dimensioned such that the depletion zone in the lightly doped region of the second doping type, which becomes larger as the blocking voltage applied to the connection electrodes increases, reaches the heavily doped region of the second doping type before the breakthrough voltage between the lightly doped region of the second doping type and the lightly doped region of the first doping type has been reached.
According to the present invention, it is of no importance whether the first doping type is a p-doping and the second doping type an n-doping or vice versa.
In the case of one embodiment of the present invention, a heavily doped region of the second doping type is provided in the lightly doped region of the first doping type between the lightly doped region of the second doping type and the heavily doped region of the first doping type, the heavily doped region of the second doping type being connected to the heavily doped region of the first doping type via the second connection electrode. The lightly doped region of the first doping type is preferably implemented as a well around the heavily doped region of the first doping type, the lightly doped region of the second doping type surrounding the well. The lightly doped region of the second doping type can be surrounded by a buried, heavily doped layer of the second doping type.
The present invention provides a device for protecting integrated circuits against electrostatic discharges (ESD) on an integrated circuit. By integrating the ESD protection device in the semiconductor substrate of the integrated circuit, an area-saving ESD protection can be achieved especially at connection points with high operating voltages exceeding e.g. 35 volts in mixed processes. It follows that the present invention provides a substantial reduction of costs in the case of integrated circuits of the type used e.g. in automobiles.